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Mixed signal designer Engineer / + de 2 ans d'expérience sur un poste similaire H/F

Corse, Bevaix Suisse (2022)
Originellement mis en ligne le 26 juillet 2022 - Remontée le 26 septembre 2022 par RecrutOr (+ d'offres)
Catherine BIAUDET Consultant Iindépendant pour Hunteed
Type de contrat :CDI
Métier :Développeur informatique
Expérience :Débutant accepté
Type d'entreprise :Autre type d'entreprise (client final)
Localisation :Corse, Bevaix Suisse (2022)
Télétravail :Pas de télétravail
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Poste à pourvoir

As a Mixed Signal Design/Verification Engineer , you will verify the mixed mode design (analog, digital and embedded software) for the Integrated Circuit (IC) based on the customer requirements.

 

More specifically, you will :

Take ownership of the digital specification and hardware-software interfaces definition for mixed-signal System-on-Chips

Make the bridge between competence centers delivering part of the SoC (Digital design, Analog design, Software design, etc.)

Work with circuit design engineers and system architects to define verification needs and create verification plans

Perform detailed simulation and verification of top level analog, digital and embedded software functionality

Be involved in the system modeling to conceptualize and validate circuits

Develop and/or integrate high-level functional models and test benches to support system simulation

Develop and/or integrate Verilog-AMS and System Verilog behavioral models Support design and production teams

 

Profil recherché

You have an engineering master degree in an electronic or microelectronic field and you have 2+ years of relevant experience as a designer in a microelectronics environment, in combination with good system verification capabilities

You have experience with the latest verification languages like System Verilog or Verilog-AMS and with scripting languages like Python, TCL, SHELL

Experience with behavioral modeling languages (Verilog, Verilog-A, Verilog-AMS, System Verilog) is an asset, as well as work experience with Cadence AMS Designer verification flow

You have experience in the UVM verification methodology Knowledge of Functional Safety industrial standards such as ISO26262 and IEC61508 is a plus

Knowledge of automotive bus interfaces SENT/SPC, PSI5 is a plus

You have experience with requirements management methodologies

Working experience in automotive industry is a plus

Experience with Git and Gitlab is an asset

You are self-driven, able to work independently while coordinating with analog, digital and software engineers

You are an efficient communicator, are fluent in English and have a customer oriented attitude

#microélectronique

#signaux numériques

#circuits intégrés à signal mixte

#logiciel embarqué

 

Points incontournables

2+ years of relevant experience as a designer in a microelectronics environment
System Verilog or Verilog-AMS
Experience with behavioral modeling languages as well as work experience with Cadence AMS Designer verification flow

Description de la société

Je vous accompagne, avec bienveillance et dans le respect du secret professionnel, à avancer par rapport à votre problématique, et ainsi vous permettre de vous sentir mieux et d'aller mieux.

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