R & D Engineer in compilation H/F
Bretagne, Rennes (35000)
Originellement mis en ligne le 16 mars 2016 - Remontée le 14 avril 2016 par Inria (+ d'offres)
Inria
Type de contrat :CDD
Métier :Informatique générale
Type d'entreprise :Autre type d'entreprise (client final)
Localisation :Bretagne, Rennes (35000)
Compétences requises :C++, Java, Programmation orientée objet, Théorie de la compilation
Poste à pourvoir
Thème de recherche : Algorithmique, programmation, logiciels et architectures
Projet : ALF
Job offer description
The hired person will be a key participant for INRIA/IRISA in the Argo project. He/she will participate to all project activities (tool development, research and supervision of research, project meetings, writing of deliverables), in close cooperation with the other persons working in the project (members of the Alf project for their expertize on WCET computation, computer architecture and compilers, members of the Cairn project for automatic parallelization and compilers).
The main activities within Argo will be the following:
- automatic code parallelization techniques, to automatically parallelize loop nests or applications developed in high-level models of computation
- code transformations and code generation techniques for tighter predictions of contentions to access shared resources (bus, network on chip, etc)
- WCET calculation for the generated parallel codes
Tools for automatic code parallelization and WCET calculation already exist at INRIA/RISA and will be extended in the course of the project.
Projet : ALF
Job offer description
The hired person will be a key participant for INRIA/IRISA in the Argo project. He/she will participate to all project activities (tool development, research and supervision of research, project meetings, writing of deliverables), in close cooperation with the other persons working in the project (members of the Alf project for their expertize on WCET computation, computer architecture and compilers, members of the Cairn project for automatic parallelization and compilers).
The main activities within Argo will be the following:
- automatic code parallelization techniques, to automatically parallelize loop nests or applications developed in high-level models of computation
- code transformations and code generation techniques for tighter predictions of contentions to access shared resources (bus, network on chip, etc)
- WCET calculation for the generated parallel codes
Tools for automatic code parallelization and WCET calculation already exist at INRIA/RISA and will be extended in the course of the project.
Profil recherché
Skills and profile
Experience of applicant :
- PhD thesis
- or development experience (3 years minimum) in the areas of the project (see keywords below)
Expected technical skills :
- object-oriented programming (Java, C++), compilation
Benefits
Net monthly salary :
- >2020 Euros (health insurance included) to be defined depending on the candidate experience
Duration of position : 3 years, to start as soon as possible
Location of position : INRIA/IRISA, Campus de Beaulieu, Rennes
Additional information
TO APPLY :
Contacts :
Interested candidates should send CV, motivation letter, and references directly to:
• Isabelle Puaut, Steven Derrien (Isabelle.Puaut@irisa.fr, Steven.Derrien@irisa.fr)
Application material :
• CV
• Letter of motivation
• Recommendation letters and/or contacts
Security and defense procedure
In the interests of protecting its scientific and technological assets, Inria is a restricted-access establishment. Consequently, it follows special regulations for welcoming any person who wishes to work with the institute. The final acceptance of each candidate thus depends on applying this security and defense procedure.
Experience of applicant :
- PhD thesis
- or development experience (3 years minimum) in the areas of the project (see keywords below)
Expected technical skills :
- object-oriented programming (Java, C++), compilation
Benefits
Net monthly salary :
- >2020 Euros (health insurance included) to be defined depending on the candidate experience
Duration of position : 3 years, to start as soon as possible
Location of position : INRIA/IRISA, Campus de Beaulieu, Rennes
Additional information
TO APPLY :
Contacts :
Interested candidates should send CV, motivation letter, and references directly to:
• Isabelle Puaut, Steven Derrien (Isabelle.Puaut@irisa.fr, Steven.Derrien@irisa.fr)
Application material :
• CV
• Letter of motivation
• Recommendation letters and/or contacts
Security and defense procedure
In the interests of protecting its scientific and technological assets, Inria is a restricted-access establishment. Consequently, it follows special regulations for welcoming any person who wishes to work with the institute. The final acceptance of each candidate thus depends on applying this security and defense procedure.
Description de la société
About Inria and the job
WCET-aware parallelization of applications for many-core architectures
Inria, the French National Institute for computer science and applied mathematics, promotes “scientific excellence for technology transfer and society”. Graduates from the world’s top universities, Inria's 2,700 employees rise to the challenges of digital sciences. With its open, agile model, Inria is able to explore original approaches with its partners in industry and academia and provide an efficient response to the multidisciplinary and application challenges of the digital transformation. Inria is the source of many innovations that add value and create jobs.
Scientific context
Safety-critical systems (e.g. avionics, medical devices, automotive, ...) have so far used simple uni-core hardware systems in order to control their predictability, in order to meet timing constraints. Still, many critical embedded systems have increasing demand in computing power, and simple uni-core processors are not sufficient anymore. General-purpose multi-core processors are not suitable for safety-critical real-time systems, because they include complex micro-architectural elements (cache hierarchies, branch, stride and value predictors) meant to improve average-case performance, and for which worst-case performance (worst-case execution times, WCET) is difficult to predict.
Some architectures were designed with both performance and predictability in mind, and are good candidates to run critical real-time software. Examples of such architectures are the Kalray MPPA many-core architecture (http://www.kalrayinc.com) or the Recore many-core hardware (http://www.recoresystems.com/).
The work will take place within the Argo H2020 project, to be started on January, 2016. The overall objective of Argo is ARGO is to define WCET-aware automatic parallelization by a cross-layer programming approach combining automatic tool-based and user-guided parallelization to reduce the need for expertise in programming parallel heterogeneous architectures.
Site web : http://www.inria.fr/
WCET-aware parallelization of applications for many-core architectures
Inria, the French National Institute for computer science and applied mathematics, promotes “scientific excellence for technology transfer and society”. Graduates from the world’s top universities, Inria's 2,700 employees rise to the challenges of digital sciences. With its open, agile model, Inria is able to explore original approaches with its partners in industry and academia and provide an efficient response to the multidisciplinary and application challenges of the digital transformation. Inria is the source of many innovations that add value and create jobs.
Scientific context
Safety-critical systems (e.g. avionics, medical devices, automotive, ...) have so far used simple uni-core hardware systems in order to control their predictability, in order to meet timing constraints. Still, many critical embedded systems have increasing demand in computing power, and simple uni-core processors are not sufficient anymore. General-purpose multi-core processors are not suitable for safety-critical real-time systems, because they include complex micro-architectural elements (cache hierarchies, branch, stride and value predictors) meant to improve average-case performance, and for which worst-case performance (worst-case execution times, WCET) is difficult to predict.
Some architectures were designed with both performance and predictability in mind, and are good candidates to run critical real-time software. Examples of such architectures are the Kalray MPPA many-core architecture (http://www.kalrayinc.com) or the Recore many-core hardware (http://www.recoresystems.com/).
The work will take place within the Argo H2020 project, to be started on January, 2016. The overall objective of Argo is ARGO is to define WCET-aware automatic parallelization by a cross-layer programming approach combining automatic tool-based and user-guided parallelization to reduce the need for expertise in programming parallel heterogeneous architectures.
Site web : http://www.inria.fr/